Advances in semiconductor chip fabrication and packaging technologies have enabled the development of highly integrated semiconductor chips and compact chip package structures or electronic modules. For example, silicon integrated circuit chips can be fabricated with high integration density and functionality to form what is referred to as SoC (System on Chip). With SoC designs, the functionality of a complete system (e.g., computer) is integrated on a single silicon die. SoC solutions may not be practical or achievable for chip-level integration when given systems design requires the use of heterogeneous semiconductor technologies to fabricate the necessary system integrated circuits.
In addition, when fabricating thinned IC devices, packages, IC stacks or package stacks, the thinned components may be fragile to handle and lead to yield losses if broken or damaged and may become non planar due to stresses such as circuits, wiring or vias causing the thinned component to bend or bow. In some cases, the bow or bending can be excessive and make handling or assembly difficult or impossible without added costs of mechanical handlers, temporary adhesives or figures and release processes.
In this regard, SIP (System In a Package) or SOP (System On a Package) techniques are used to integrate various die technologies (e.g., Si, GaAs, SiGe, SOT) to form a complete system which approximates SoC performance. By way of example, a SOP module can be constructed by mounting a plurality of semiconductor chips to a chip carrier substrate to form a first level (or chip level) package structure. In conventional packaging technologies, chip level carrier substrates are constructed using organic laminate build up or ceramic carrier substrate technologies. Typically, first level package having conductive through-vias (and other conductive wiring) which provide I/O and power interconnects between IC chips on the top-side of the carrier and I/O contacts on a next level packaging structure coupled to the bottom-side of the chip carrier.
As the number of circuits on a single chip is increased or as need rises to interconnect chips with much higher density I/O, or for miniaturization or for heterogeneous chip integration, or for integration of chips and stacked chips, the need arises for new packaging which can support higher wiring density and smaller form factors. As the number of circuits on a chip increase, higher density I/O packaging is typically needed or for heterogeneous chip or chip stack integration. However, there are disadvantages associated with organic and ceramic carrier technologies including, for example, high fabrication costs and inherent limitations the practical integration density, I/O density, power density, etc, that may be achieved using organic or ceramic carriers, as is known in the art. It is believed that inherent limitations and high fabrication costs associated with ceramic and organic carrier technologies may limit the ability or desire to use such carrier technologies to meet the increasing demands for higher density and higher performance and low cost packaging solutions.